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19-0644; Rev 2; 2/09
4-Channel I2C Switches/Multiplexer
General Description
The MAX7367/MAX7368/MAX7369 bidirectional, fourchannel I2C switches/multiplexer expand the main I2C bus up to four extended buses. The MAX7369 1:4 multiplexer connects the main I2C bus to one channel at a time. The MAX7367/MAX7368 four-channel switches connect the main I 2C bus to one or more channels at a time. These devices isolate bus loading by extending the I2C bus onto different channels. The MAX7367/MAX7368/ MAX7369 allow more devices to be interconnected to a master controller and multiple devices with the same I2C address to communicate to a master. The channels are selected through the main I2C bus by writing to the internal control register of the device. Any device connected to an I2C bus can transmit and receive signals. The MAX7367/MAX7368/MAX7369 are transparent to signals sent and received at each channel, allowing multiple masters. These devices are compatible with the I 2 C protocol of clock stretch, synchronization, and arbitration in case multiple masters address the bus at the same time. All devices are set to the default state during initial power-up. The MAX7367/MAX7368 have a RESET input allowing external circuitry to set the MAX7367/MAX7368 to its default state anytime after the device has powered up. The MAX7367/MAX7369 have interrupt inputs, allowing devices on the extended bus to send an interrupt signal to the master on the main bus. The MAX7367/MAX7369 are available in 20-pin TSSOP packages, and the MAX7368 is available in a 16-pin TSSOP package. All devices operate over the -40C to +85C extended temperature range.
Features
o Four-Channel, Bidirectional Bus Expansion o Voltage-Level Translation o Low 6A (typ) Supply Current, 0.1A (typ) Standby Current o Low 16 (typ) On-Resistance o Channel Selection Through I2C o I2C-Compatible Normal or Fast Mode o Device Address Selection Up to Four Addresses (MAX7367) Up to Eight Addresses (MAX7368/MAX7369) o Bus-Loading Isolation o Support Clock Stretch, Synchronization, and Arbitration o Hot Insertion o 2.3V to 5.5V Supply Voltage Range o 5V-Tolerant Inputs o Interrupt from Extended Buses (MAX7367/MAX7369) o Hardware Reset (MAX7367/MAX7368)
MAX7367/MAX7368/MAX7369
Ordering Information
PART MAX7367EUP+ MAX7368EUE+ TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 20 TSSOP 16 TSSOP
MAX7369EUP+ -40C to +85C 20 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configurations
TOP VIEW
A0 1 A1 2 RESET 3 INT0 4 SD0 5 SC0 6 INT1 7 SD1 8 SC1 9 GND 10
Applications
Servers RAID Cellular Phones Base Stations PCs Multimedia Electronics SAN/NAS
+
20 VDD 19 SDA 18 SCL
MAX7367
17 INT 16 SC3 15 SD3 14 INT3 13 SC2 12 SD2 11 INT2
TSSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
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4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +6.0V All Other Pins to GND............................................-0.3V to +6.0V Input Currents VDD ...............................................................................100mA GND ..............................................................................100mA All Input Pins.................................................................20mA Output Current ....................................................................25mA Continuous Power Dissipation (TA = +70C) 20-Pin TSSOP (derate 11.0mW/C above TA = +70C) .................................................. 879.1mW 16-Pin TSSOP (derate 9.4mW/C above TA = +70C) .................................................. 754.7mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (3.3V SUPPLY)
(VDD = 2.3V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25C.) (Note 1)
PARAMETER POWER SUPPLY Supply Voltage Standby Current VDD ISTB No load, all inputs = VDD or GND, VDD = 3.6V, all channels disabled No load, all inputs = VDD or GND, fSCL = 100kHz, VDD = 3.6V, all channels disabled VDD rising 2.3 0.1 3.6 1 V A SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current Power-On-Reset (POR) Voltage Power-On-Reset Hysteresis
IDD
6
30
A
VPOR VHYST
1.4 0.4
2.1
V V
INPUT SCL, INPUT/OUTPUT SDA Low-Level Input Voltage High-Level Input Voltage Low-Level Output Current Input Leakage Current Input Capacitance VIL VIH IOL IL CI All inputs = GND VOL = 0.4V VOL = 0.6V (Note 2) -0.2 0.7 x VDD 3 6 -1 15 +0.3 x VDD 5.5 +1 5 30 50 +1 +0.3 x VDD 5.5 V V mA A pF
SELECT INPUTS A2, A1, A0, INT0-INT3, RESET Low-Level Input Voltage High-Level Input Voltage Input Leakage Current Input Capacitance VIL VIH IL CI All inputs = GND (Note 2) -0.2 0.7 x VDD -1 V V A pF
2
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4-Channel I2C Switches/Multiplexer
ELECRTICAL CHARACTERISTICS (3.3V SUPPLY) (continued)
(VDD = 2.3V to 3.6V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25C.) (Note 1)
PARAMETER PASS GATE Switch On-Resistance RON VDD = 3V to 3.6V, IO = 15mA, VO = 0.4V VDD = 2.3V to 2.7V, IO = 10mA, VO = 0.4V VI(SW) = VDD = 3.0V to 3.6V, IO = -100A Switch Output Voltage Leakage Current Input/Output Capacitance INT OUTPUT Low-Level Output Current High-Level Output Current IOL IOH VOL = 0.4V 3 1 mA A VPASS IL CIO All inputs = GND VI(SW) = VDD = 2.3V to 2.7V, IO = -100A VI(SW) = VDD = 2.5V, IO = -100A -1 6 5 7 1.6 1.1 1.5 +1 A pF 16 23 1.9 30 55 2.8 2.0 V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX7367/MAX7368/MAX7369
ELECRTICAL CHARACTERISTICS (5V SUPPLY)
(VDD = 4.5V to 5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 5V, TA = +25C.) (Note 1)
PARAMETER POWER SUPPLY Supply Voltage Standby Current Supply Current Power-On-Reset Voltage POR Hysteresis VDD ISTB IDD VPOR VHYST No load, all inputs = VDD or GND, VDD = 5.5V, all channels disabled No load, all inputs = VDD or GND, fSCL = 100kHz, VDD = 5.5V, all channels disabled VDD rising 4.5 0.3 12 1.4 0.4 +0.3 x VDD 5.5 30 50 +1 15 +0.3 x VDD 5.5 5.5 1 50 2.1 V A A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT SCL, INPUT/OUTPUT SDA Low-Level Input Voltage High-Level Input Voltage Low-Level Output Current Input Leakage Current Input Capacitance VIL VIH IOL IL CI All inputs = GND VOL = 0.4V VOL = 0.6V (Note 2) -0.2 0.7 x VDD 3 6 -1 V V mA A pF
SELECT INPUTS A2, A1, A0, INT0-INT3, RESET Low-Level Input Voltage High-Level Input Voltage VIL VIH (Note 2) -0.2 0.7 x VDD V V
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3
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
ELECRTICAL CHARACTERISTICS (5V SUPPLY) (continued)
(VDD = 4.5V to 5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = 5V, TA = +25C.) (Note 1)
PARAMETER Input Leakage Current Input Capacitance PASS GATE Switch On-Resistance Switch Output Voltage Leakage Current Input/Output Capacitance INT OUTPUT Low-Level Output Current High-Level Output Current IOL IOH VOL = 0.4V 3 1 mA A RON VPASS IL CIO All inputs = GND VDD = 4.5V to 5.5V, IO = 15 mA, VO = 0.4V VI(SW) = VDD, IO = -100A 4 2.6 -1 6 12 3.6 24 4.5 +1 V A pF SYMBOL IL CI All inputs = GND CONDITIONS MIN -1 5 TYP MAX +1 UNITS A pF
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Propagation Delay from SDA To SD_ or SCL to SC_ SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (after this period, the first clock pulse is generated) Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Setup Time for STOP Condition Data Hold Time (Note 4) Data Setup Time Rise Time of Both SDA and SCL Signals SYMBOL tpd fSCL tBUF fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz tHD;STA fSCL = 400kHz tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz fSCL = 400kHz fSCL = 100kHz tr fSCL = 400kHz (Note 5) 20 + 0.1Cb 0.6 4.7 1.3 4.0 0.6 4.7 0.6 4.0 0.6 0 0 250 100 1000 300 ns 3.45 0.9 s s s s s ns (Note 3) 0 4.7 1.3 4.0 s CONDITIONS MIN TYP MAX 0.3 400 UNITS ns kHz s
4
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4-Channel I2C Switches/Multiplexer
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.3V to 5.5V, TA = -40C to +85C, unless otherwise noted.) (Note 1)
PARAMETER Fall Time of Both SDA and SCL Signals Capacitive Load for Each Bus Line Pulse Width of Spikes Suppressed Data Valid Time from High to Low Data Valid Time from Low to High Data Valid Acknowledge INT (Figure 2) INT_ to INT Active Valid Time INT_ to INT Inactive Delay Time Low-Level, Pulse-Width Rejection or INT_ Inputs High-Level, Pulse-Width Rejection or INT_ Inputs RESET (Figure 3) Pulse-Width Low Reset Reset Time (SDA Clear) Recovery to Start tWL(RST) tRST tREC;STA 500 0 4 ns ns ns tIV tIR tW(REJ)L tW(REJ)H 1 0.5 4 2 s s s s SYMBOL tf Cb tSP tVD;DATL tVD;DATH tVD;ACK (Note 7) (Note 7) CONDITIONS fSCL = 100kHz fSCL = 400kHz (Note 5) (Note 6) 20 + 0.1Cb MIN TYP MAX 300 300 400 50 1 0.6 1 ns pF ns s s s UNITS
MAX7367/MAX7368/MAX7369
Note 1: Note 2: Note 3: Note 4:
All parameters are production tested at TA = +25C and guaranteed by design over the specified temperature range. Minimum value is not production tested. Guaranteed by design. Pass gate propagation delay is calculated from 20 (typ) RON and the 15pF load capacitance. Not production tested. A master device must provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL) in order to bridge the undefined region of SCL's falling edge. Note 5: Cb = total capacitance of one bus line in pF. Note 6: Guaranteed by design. Note 7: Measurements taken with a 1k pullup resistor and 50pF load.
SDA tf tLOW tr tSU;DAT tf tHD;STA tSP tr tBUF
SCL tHD;STA S tHIGH tSU;STA Sr tSU;STO P S
tHD;DAT
Figure 1. 2-Wire Serial-Interface Timing Diagram
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4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
INT_
50%
50%
tIV
tW(REJ)L
tW(REJ)H
tIR 50%
INT
50%
Figure 2. INT Timing Diagram
SCL
SDA
tREC;STA
tRST
RESET
tWL(RST)
Figure 3. RESET Timing Diagram
6
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4-Channel I2C Switches/Multiplexer
Typical Operating Characteristics
(VDD = +5V, TA = +25C, unless otherwise noted.)
PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX7367 toc01
MAX7367/MAX7368/MAX7369
VPASS VOLTAGE vs. SUPPLY VOLTAGE
MAX7367 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
70 SUPPLY CURRENT (A) 60 50 40 30 20 10 0 SCL = 100kHz AND SDA = 0V SCL = 400kHz AND SDA = 0V
MAX7367 toc03
7 fIN = 400kHz 6 PROPAGATION DELAY (ns) 5 4 3 2 RISING EDGE 1 0 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 FALLING EDGE
4.5 4.0 3.5 3.0 VPASS (V) 2.5 2.0 1.5 1.0 0.5 0
80
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SCL FREQUENCY
VDD = 5V AND SDA = 0V 50 SUPPLY CURRENT (A) 40 30 20 10 0 100 150 200 250 300 350 400 FREQUENCY (kHz)
MAX7367 toc04
60
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7
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
Pin Description
PIN MAX7367 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 -- 17 18 19 20 MAX7368 1 2 3 -- 4 5 -- 6 7 8 -- 9 10 -- 11 12 13 -- 14 15 16 MAX7369 1 2 -- 4 5 6 7 8 9 10 11 12 13 14 15 16 3 17 18 19 20 NAME A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 GND INT2 SD2 SC2 INT3 SD3 SC3 A2 INT SCL SDA VDD Device Address Bit 0 (LSB) Device Address Bit 1 Active-Low Reset Input Channel 0 Active-Low Interrupt Input. A logic-low INT0 asserts INT. If not used, pull up INT0 through a resistor to VDD. Channel 0 Serial Data Channel 0 Serial Clock Channel 1 Active-Low Interrupt Input. A logic-low INT1 asserts INT. If not used, pull up INT1 through a resistor to VDD. Channel 1 Serial Data Channel 1 Serial Clock Ground Channel 2 Active-Low Interrupt Input. A logic-low INT2 asserts INT. If not used, pull up INT2 through a resistor to VDD. Channel 2 Serial Data Channel 2 Serial Clock Channel 3 Active-Low Interrupt Input. A logic-low INT3 asserts INT. If not used, pull up INT3 through a resistor to VDD. Channel 3 Serial Data Channel 3 Serial Clock Device Address Bit 2 Active-Low, Open-Drain Interrupt Output. Connect a pullup resistor to VDD. Main Serial Clock Main Serial Data Power Supply. Bypass to GND with 0.1F capacitor. FUNCTION
8
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4-Channel I2C Switches/Multiplexer
MAX7367 Functional Diagram
MAX7367/MAX7368/MAX7369
SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3
SWITCH CONTROL LOGIC
RESET VDD
POWER-ON RESET
MAX7367
SCL GLITCH FILTER SDA
I2C BUS CONTROL
A0 A1
INT[0-3]
INTERRUPT LOGIC
INT GND
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9
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
MAX7368 Functional Diagram
SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3
SWITCH CONTROL LOGIC
RESET VDD
POWER-ON RESET
MAX7368
SCL GLITCH FILTER SDA
I2C BUS CONTROL
A0 A1 A2 GND
10
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4-Channel I2C Switches/Multiplexer
MAX7369 Functional Diagram
MAX7367/MAX7368/MAX7369
SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3
SWITCH CONTROL LOGIC
VDD
POWER-ON RESET
MAX7369
SCL GLITCH FILTER SDA
I2C BUS CONTROL
A0 A1 A2
INT[0-3]
INTERRUPT LOGIC
INT GND
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11
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
Detailed Description
The MAX7367/MAX7368/MAX7369 bidirectional, fourchannel I2C switches/multiplexer expand the main I2C bus up to four extended buses. The MAX7369 is a 1:4 multiplexer that connects the main I2C bus to one channel at a time. The MAX7367/MAX7368 are four-channel switches that can connect the main I2C bus to one or more channels at a time. These devices isolate bus loading by separating available I2C devices into groups on the channels. The total loading capacitance of the main bus plus those of the connected channel must not exceed 400pF. The extended buses are connected or disconnected through the main I2C bus by writing to the control register of the MAX7367/MAX7368/MAX7369. Any device connected to an I2C bus can transmit and receive signals. The MAX7367/MAX7368/MAX7369 are transparent to signals sent and received at each channel, allowing multiple masters on the buses. These devices are compatible with the I2C protocol of clock stretch, synchronization, and arbitration in case of multiple masters addressing the bus at the same time. The MAX7367/MAX7368 have a RESET input that allows external circuitry to set the MAX7367/MAX7368 to its default state anytime after the device has powered up. The MAX7367/MAX7369 have interrupt inputs, allowing devices on the extended bus to send an interrupt signal to the master on the main bus. master bus sends a byte or the master bus receives a byte from/to the MAX7367/MAX7368/MAX7369. The last 3 bits (for the MAX7369) or 4 bits (for the MAX7367/ MAX7368) of the byte are stored in the control/interrupt register (B0 to B2 or B0 to B3) for channel selection. If multiple bytes are received, only the last byte received is saved. The first four bits of the register represent the interrupt condition (for the MAX7367/MAX7369 only).
1
1
1
0
0
A1
A0
R/W
FIXED
HARDWARE SELECTION
Figure 4. MAX7367 Slave Address
1
1
1
0
A2
A1
A0
R/W
FIXED
HARDWARE SELECTION
Device Address
The MAX7367/MAX7368/MAX7369 have selectable device addresses through external inputs. The MAX7367 slave address consists of 5 fixed bits (A6-A2, set to 11100), followed by 2 pin-programmable bits (A1 and A0), as shown in Figure 4. The MAX7368/ MAX7369 slave address consists of 4 fixed bits (A6-A3, set to 1110), followed by 3 pin-programmable bits (A2, A1 and A0), as shown in Figure 5. The most significant address bit (A6) is transmitted first, followed by the remaining bits. The addresses A2 (for MAX7368/ MAX7369), A1, and A0 can also be driven dynamically if required, but the values must be stable when they are expected in the address sequence.
Figure 5. MAX7368/MAX7369 Slave Address
INTERRUPT BITS (READ ONLY) 7 INT3 6 INT2 5 INT1 4 INT0
CHANNEL SELECTION BITS (READ/WRITE) 3 B3 2 B2 1 B1 0 B0 CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 INT0 INT1 INT2 INT3
Control/Interrupt Register
There is a control/interrupt register inside the MAX7367/ MAX7369 (Figures 6 and 8). There is a control (only) register inside the MAX7368 (Figure 7). Use the main I2C bus to write or read from this register. Following the successful acknowledgement of the slave address, the
Figure 6. MAX7367 Control/Interrupt Register
12
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4-Channel I2C Switches/Multiplexer
After a device generates an interrupt on one of the channels, the interrupt input is loaded into the control/interrupt register when a read is performed. To determine which device is generating the interrupt, read the contents of the control/interrupt register to determine which channel is issuing the interrupt, then write the appropriate command to the control/interrupt register to select the interrupted channel. Read from all devices on the interrupted channel to determine the exact source of the interrupt.
MAX7367/MAX7368/MAX7369
CHANNEL SELECTION BITS (READ/WRITE) 7 X 6 X 5 X 4 X 3 B3 2 B2 1 B1 0 B0 CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3
X = DON'T CARE.
Figure 7. MAX7368 Control Register
Table 1. MAX7367/MAX7368 Control Bits for Channel Selection
CONTROL BIT COMMAND 0 = Channel 0 disabled (default) 1 = Channel 0 enabled 0 = Channel 1 disabled (default) 1 = Channel 1 enabled 0 = Channel 2 disabled (default) 1 = Channel 2 enabled 0 = Channel 3 disabled (default) 1 = Channel 3 enabled
CHANNEL SELECTION BITS (READ/WRITE)
INTERRUPT BITS (READ ONLY) 7 INT3 6 INT2 5 INT1 4 INT0 3 X
B0 B1 B2
2 B2
1 B1
0 B0
ENABLE BIT X = DON'T CARE.
B3
Figure 8. MAX7369 Control/Interrupt Register
Channel Selection Each channel selected contains an SD_ and SC_ pair. Select a channel by writing a control byte after a successful acknowledge of the slave address. The last 4 bits of the control byte determine which channel(s) is selected for the MAX7367/MAX7368 as shown in Table 1. The last 3 bits of the control byte determine which channel is selected for the MAX7369 as shown in Table 2. The selected channels are activated after the stop condition. When a channel is selected, the respective SD_/SC_ pair is logic-high, ensuring no false conditions occur on the bus. Interrupt Logic (MAX7367/MAX7369) The MAX7367/MAX7369 have four interrupt inputs, one for each channel, and one INT output. The INT output is an open-drain output that requires a pullup resistor. The INT output is asserted by a low-logic signal on any of the INT_ inputs, and it is deasserted only when all the INT_ inputs are logic-high. Bits 4-7 of the MAX7367/MAX7369 control/interrupt register store the state of the INT_ for each channel as shown in Table 3 and Figures 6 and 8. The logic level of INT_ is not latched. Drive the respective INT_ input high to remove the interrupt condition for the channel. An interrupt can occur on any channel, regardless of whether it is selected or not selected.
Table 2. MAX7369 Control Bits for Channel Selection
B2 0 0 1 1 1 1 B1 0 X 0 0 1 1 B0 0 X 0 1 0 1 COMMAND No channel selected (default) No channel selected Channel 0 selected Channel 1 selected Channel 2 selected Channel 3 selected
Table 3. MAX7367/MAX7369 Interrupt Indicator Bits
INTERRUPT BIT INT0 INT1 INT2 INT3 STATE 0 = No channel 0 interrupt (default) 1 = Channel 0 interrupt 0 = No channel 1 interrupt (default) 1 = Channel 1 interrupt 0 = No channel 2 interrupt (default) 1 = Channel 2 interrupt 0 = No channel 3 interrupt (default) 1 = Channel 3 interrupt
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13
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
RESET Input (MAX7367/MAX7368)
The MAX7367/MAX7368 feature an active-low RESET input. When RESET is driven low for more than 4ns, the MAX7367/MAX7368 reset the internal register and I2C state machine to their default states, allowing a master to recover from a bus fault condition. high period of the clock pulse (Figure 11). In the case of an unsuccessful data transfer, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
Power-On Reset (POR)
When power is applied to VDD, internal POR circuitry holds the MAX7367/MAX7368/MAX7369 in a reset state until VDD has reached the VPOR threshold. At this point, the reset condition is released, and the MAX7367/ MAX7368/MAX7369 register and I2C state machine are initialized to their default states (all zeroes), causing all the channels to be deselected.
Voltage Translation
The MAX7367/MAX7368/MAX7369 can be used as a voltage translator from the main bus to the extended buses. The output voltage (VPASS) is limited by the supply voltage (VDD) (see the Typical Operation Characteristics). For the MAX7367/MAX7368/MAX7369 to be used as a voltage translator, the VPASS voltage should be lower than or equal to the lowest bus voltage.
SDA
SCL DATA STABLE DATA VALID CHANGE OF DATA ALLOWED
I2C Interface
The MAX7367/MAX7368/MAX7369 feature an I2C-compatible, 2-wire serial interface consisting of a bidirectional serial-data line (SDA) and a serial-clock line (SCL). The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL.
Figure 9. Bit Transfer
SDA
Bit Transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable while SCL is high (Figure 9). Start and Stop Conditions Both SCL and SDA remain high when the interface is not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning the SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 10). Acknowledge Bit Successful data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (NA). Both the master and the MAX7367/MAX7368/MAX7369 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the
14
SCL
S
P STOP CONDITION
START CONDITION
Figure 10. Start and Stop Conditions
START CONDITION SCL 1 2
CLOCK PULSE FOR ACKNOWLEDGMENT 8 NOT ACKNOWLEDGE 9
SDA ACKNOWLEDGE
Figure 11. Acknowledge
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4-Channel I2C Switches/Multiplexer
Serial Addressing A master initiates communication with a slave device by issuing a START condition followed by a slave address byte. The slave address byte consists of 7 address bits and a read/write bit (R/W). When idle, the MAX7367/MAX7368/MAX7369 continuously wait for a START condition followed by its slave address. After recognizing a start condition followed by the correct address, the MAX7367/MAX7368/MAX7369 are ready to accept or send data. The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX7367/MAX7368/ MAX7369 (R/W = 0 selects a write command, R/W = 1 selects a read command as shown in Figures 12 and 13). After receiving the proper address, the MAX7367/MAX7368/MAX7369 (slave) issue an ACK by pulling SDA low for one clock cycle.
Applications Information
Repeated Slave Addresses
The MAX7367/MAX7368/MAX7369 allow systems to reuse slave addresses individually on each channel of the extended bus. To reuse slave addresses on the extended bus channels of the MAX7367/MAX7368, ensure no more than one channel with a reused address is selected at the same time.
MAX7367/MAX7368/MAX7369
Power-Supply Considerations
The MAX7367/MAX7368/MAX7369 operate from a +2.3V to +5.5V power-supply voltage. Good powersupply decoupling is needed to maintain the performance of these parts. Bypass VDD to GND with a 0.1F surface-mount ceramic capacitor. Mount the bypass capacitor as close as possible to the device.
START CONDITION
ACKNOWLEDGE BIT FROM SLAVE 0 (A2) A1 A0 1 A INT3* INT2* INT1* INT0* B3** B2
STOP CONDITION
S
1
1
1
B1
B0
NA
P
DEVICE ADDRESS () A2 = 0 FOR MAX7367. ** DON'T CARE FOR MAX7368. ** DON'T CARE FOR MAX7369.
CONTROL BYTE
NOT ACKNOWLEDGE BIT FROM MASTER
Figure 12. Read Command
START CONDITION
ACKNOWLEDGE BIT FROM SLAVE 0 (A2) A1 A0 0 A X X X X B3* B2
STOP CONDITION
S
1
1
1
B1
B0
A
P
DEVICE ADDRESS () A2 = 0 FOR MAX7367. * DON'T CARE FOR MAX7369. X = DON'T CARE.
CONTROL BYTE
ACKNOWLEDGE BIT FROM SLAVE
Figure 13. Write Command
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15
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
Choosing Pullup Resistors
I2C requires pullup resistors to provide a logic-high level to data and clock lines. There are tradeoffs between power dissipation and speed, and a compromise must be made in choosing pullup resistor values. Every device connected to the bus introduces some capacitance even when the device is not in operation. I2C specifies 300ns rise times to go from low to high (30% to 70%) for fast mode, which is defined for a data rate of 400kbps (refer to I2C specifications for details). In order to meet the rise time requirement, choose the pullup resistors such that the rise time (t R = 0.85RPULLUP x CBUS) is less than 300ns. For a bus capacitance of 400pF, choose a pullup resistor less than 880. Often I2C devices work when the maximum specified rise time is exceeded. However, if the rise times become too slow, the devices on the bus do not recognize the command signals. Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines and also minimize crosstalk and undershoot of the bus signals.
Chip Information
PROCESS: BiCMOS
Pin Configurations (continued)
TOP VIEW +
A0 1 A1 2 RESET 3 SD0 4 SC0 5 SD1 6 SC1 7 GND 8 16 VDD 15 SDA 14 SCL A0 1 A1 2 A2 3 INT0 4 SD0 5 SC0 6 INT1 7 SD1 8 SC1 9 GND 10
+
20 VDD 19 SDA 18 SCL
MAX7369
17 INT 16 SC3 15 SD3 14 INT3 13 SC2 12 SD2 11 INT2
MAX7368
13 A2 12 SC3 11 SD3 10 SC2 9 SD2
TSSOP
TSSOP
16
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
Typical Operating Circuit
VCC VDD VDD
MAX7367/MAX7368/MAX7369
VDD SDA SCL MASTER (INT) RESET * (INT0) VDD SDA SCL SD0 SC0
MAX7367 MAX7368 MAX7369
SD1 SC1 (INT1) VDD
SD2 SC2 (INT2) VDD
A0 A1 A2** GND * FOR MAX7367/MAX7368. ** FOR MAX7368/MAX7369. () FOR MAX7367/MAX7369. SD3 SC3 (INT3)
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17
4-Channel I2C Switches/Multiplexer MAX7367/MAX7368/MAX7369
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 20 TSSOP 16 TSSOP PACKAGE CODE U20-3 U16-1 DOCUMENT NO. 21-0066 21-0066
18
______________________________________________________________________________________
4-Channel I2C Switches/Multiplexer
Revision History
REVISION 0 1 2 REVISION 10/06 12/06 2/09 DESCRIPTION Initial release of the MAX7369 Initial release of the MAX7367/MAX7368 Changed the minimum VIL spec PAGES CHANGED -- 1 2-5
MAX7367/MAX7368/MAX7369
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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